One or more aspects of the present invention relate to processor simulation, and more specifically, to verifying architectural compliance of a processor core using processor-sparing functions of the processor core.
When developing new processor architectures or any other processor containing unit, a design of the new processor core is tested to debug it. This test is performed in a pre-silicon phase and a post-silicon phase. In the pre-silicon phase, the processor is simulated in a simulation environment. For debugging the processor, random errors are injected into a model of the processor. This phase takes a lot of time since many possible errors exist and the model is not always able to correct for the errors by itself. In such a case, the model has to be reset and restarted.
The existing methodology for verifying architectural compliance of the processor core using sparing functions requires a simulated processor core model to recover from any occurred or simulated error. Therefore, several hardware features, i.e. refreshes, error scan logouts and logic resets, need to be stable in order to recover from the injected error before the architectural compliance can be checked. The recovery itself takes many cycles, thus increasing the runtime of the simulation and the time to find a bug and debug it.